/*  ROM boot program  */
/***     Memory Map   ***/
/*
 *  FFFFFF   +------------------------+
 *           |                        |
 *    to     |   TPU, QSM, SIM        |
 *           |                        |
 *  FFF000   +------------------------+
 *
 *  0C0000   +------------------------+
 *           |    Stack (4k)          |
 *           +------------------------+
 *           |                        |
 *           | Inputs, constants,     |
 *           | tables, variables      |
 *           | (room for ~60k)        |
 *           |                        |
 *  0B0800   +------------------------+
 *           |  vbr, exception        |
 *           |  tables (need 1k,      |
 *           |    allow 2k)           |
 *  0B0000   +------------------------+
 *           |                        |
 *           |     EFI Code           |
 *           |  (room for ~190k)      |
 *           |                        |
 *           |                        |
 *           | SRAM=080000 to         |
 *           | 0C0000 (256k)          |
 *  080000   +------------------------+
 *
 *  040000   +------------------------+
 *           |   EEPROM (256k)        |
 *           |                        |
 *           |                        |
 *           |                        |
 *  000400   |  Start ROM Pgm         |
 *           |   (see note)           |
 *           |                        |
 *           |Err & intrpt vectrs     |
 *           |                        |
 *  000004   | Reset PC(=000400)      |
 *  000000   | Reset SP(=FFFFFF(tpu)) |
 *           +------------------------+
 *
 *   Note: load this program at $A03FC in SRAM so that pgm will
 *   start at $A0400 without the link a6, #0; don't want link,
 *   since have not yet configured SRAM/ set true stack.
 */
   
    struct simregs {                  /* sim registers */
      volatile unsigned short int sreg[59];
    };
    #define sr (*(struct simregs *)0xFFFA00)   /* address of 1st sim reg */
      
    rom_start()
    {

    /* Disable interrupts, locate VBR and stack pointer */
     asm volatile ("moveal #0x0B0000, %a0;
		    movec %a0, %vbr;
		    moveal #0x0C0000, %sp");
  
    /* Set SYPCR = 0 to disable SW watchdog timer (can turn on later if need) */
     sr.sreg[16] = 0;

    /* Zero out (set low) port C data latches */
     sr.sreg[32] = 0;

    /* Locate ROM: base addr = 0; blksize = 256k  */
     sr.sreg[36] = 0x0005;    /* CSBOOT */
     sr.sreg[58] = 0x0005;    /* CS10 */

    /* Locate SRAM: base addr = 080000; blksize = 256k  */
     sr.sreg[38] = 0x0805;    /* CS0 */
     sr.sreg[40] = 0x0805;    /* CS1 */
     sr.sreg[42] = 0x0805;    /* CS2 */

    /* CS Options: all asynchronous, strb= AS, U/S space, no ipl/ avec  */
      /* Note: waits = int(access time(ns)/ (1/ freq)) + 1. For 16.777 MHz
	(59.6054 ns) with 70 ns SRAM, use 2 wait states; need 3 waits for 
	120 ns SRAM.  */
 /*  sr.sreg[37] = 0x68B0; */ /* CSBOOT(ROM- both bytes,read,2 waits) */
     sr.sreg[37] = 0x68F0;    /* CSBOOT(ROM- both bytes,read,3 waits) */
     sr.sreg[39] = 0x6BF0;    /* CS0(SRAM OE- both bytes,read,external) */
		 /* Need external because this not "true" CS. Don't want
	            it to change state before real bus cycle on CS1/2. */
     sr.sreg[41] = 0x38F0;    /* CS1 (SRAM- lowr byte,r & w,3 waits) */
     sr.sreg[43] = 0x58F0;    /* CS2 (SRAM- uppr byte,r & w,3 waits) */
 /*  sr.sreg[41] = 0x38B0; */ /* CS1 (SRAM- lowr byte,r & w,2 waits) */
 /*  sr.sreg[43] = 0x58B0; */ /* CS2 (SRAM- uppr byte,r & w,2 waits) */
     sr.sreg[59] = 0x6BF0;    /* CS10 (ROM OE- both bytes,read,external) */
		 /* Need external because this not "true" CS. Don't want
	            it to change state before real bus cycle on CSBOOT. */

    /* Set CS pin assignments  */
     sr.sreg[34] = 0x00FF;    /* CSBOOT is 16-bit boot chip select to ROM;
			          CS0 is 16-bit chip select to OE on SRAM;
	             CS1,CS2 are 16-bit lower, upper chip selects to SRAM;
				          rest are 00 = discrete o/p pins */
     sr.sreg[35] = 0x0300;      /* CS10 is 16-bit chip select to OE on ROM;
				          rest are 00 = discrete o/p pins */

    /* Set cpu status reg to supv, int mask=001 (in status register) */
     asm ( "MOVE.W #0x2100, %SR");
     asm ( "BRA.L $80000");        /* go to sram */
	 /* Note: BRA is relative to current pc; therefore, must adjust
	    displacement from pc in ROM. Do this manually after loaded. */
     exit();

    }