P4 chipset memory map

Memory location	Purpose
0x0000-0x00ff	Battery backed static ram
0x0100-0x01ff	Non-battery backed static ram, cleared when the key is off
0x0200-0x03ff	On chip SRAM in enhanced P4 MPUs
0x0400-0x04ff	GM debugging HUD ram variables (if present)
0x3dc0-0x3dff	Extra timer chip
0x3f80-0x3fbf	Extra timer chip
0x3fc0-0x3fff	P4 timer chip
0x4000-0x400f	memory mapped I/O registers
0x5000-0x5fff	GM debugging HUD hardware
0x5800-0x58ff	GM debugging HUD code
0x6000-0x6fff	GM debugging HUD code
0xc000-0xffff	EPROM (27128, 16K EPROM, code and data)
0x8000-0xffff	EPROM (27256, 32K EPROM, code and data)
0xfff0-0xfffe	interrupt vectors

I/O registers

r/w $4000 SPI data register
r/w $4001 I/O control register, including SPI control
r/w $4002 I/O port (probably all outputs)
- %10000000 chip select to output only SPI device
- %01000000 chip select to in and out SPI device
- %00001000 chip select to SPI interfaced ADC
- %00000100 chip select to in and out SPI device
- %00000010 IAC phase B output
- %00000001 IAC phase A output
r/w $4003 DDR, probably for $4004
r/w $4004 I/O port
- %00000100 Enable IAC
ro $4005 Free running up counter, probably at 32768 Hz
r/w $4006 Interrupt time, IRQ when $4006 == $4005 ( maybe <= )
r/w $4007 SCI control register
ro $4008 Interrupt source flags
- %10000000 TDRE
- %01000000 TC
- %00100000 RDRF
- %00010000 ?
- %00001000 overrun
- %00000100 noise flag
- %00000010 framing error
- %00000001 IRQ flag
ro $4009 SCI RxD register
wo $400A SCI TxD register
wo $400B COP watchdog ($FF)
wo $400C COP watchdog ($00)

Interrupt vectors

0xfff0 -- SWI instruction
0xfff2 -- Internal int (UART and periodic interrupt)
0xfff4 -- External interrupt
0xfff6 -- Illegal instruction
0xfff8 -- Bus reset (any read or write to 0x6000-0x6fff)
0xfffa -- Watchdog reset
0xfffc -- Clock monitor reset
0xfffe -- Power on and external reset